| Title | Iterative Search for Reconfigurable Accelerator Blocks with a Compiler in the Loop |
| Publication Type | Journal Article |
| Year of Publication | 2018 |
| Authors | Willsey M., Lee V.T, Cheung A., Bodík R., Ceze L. |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Pagination | 1–1 |
| ISSN | 0278-0070 |
| Keywords | Computer architecture, DSL, Field programmable gate arrays, Genetic algorithms, Hardware, Python, Tools |
| Abstract | Domain-specific reconfigurable accelerators (DSRAs) achieve high performance and energy efficiency by using specialized processing elements (PEs) instead of general-purpose alternatives. However, the process of designing, selecting, and refining the reconfigurable PEs that compose the accelerator fabric has remained a manual and difficult task. This paper presents Reconfigurable Accelerator Design using Iterative Search for Hardware (RADISH) which is a full-stack framework for automatically identifying and generating PEs from an application corpus. RADISH uses a genetic algorithm to iteratively search for and refine the proposed PEs with a compiler-in-the-loop to guide the search. We show that RADISH-generated PEs can generalize to both larger instances of the same application as well as other previously unseen applications within the same domain. We evaluate a CGRA architecture using our RADISH-generated PEs and show it achieves a geometric mean improvement of up to 2.14× and 2.4× power and area respectively over an ALU-based CGRA designs. In terms of energy, our generated designs achieve a geometric mean improvement of 2.5× but can achieve gains up to 28.9×. |
| DOI | 10.1109/TCAD.2018.2878194 |
| Citation Key | cgra-tcad18 |
